Integrated circuits are formed within a semiconductor wafer by using a series of well-known techniques such as thin film deposition, diffusion, ion implantation, etc. in combination with photolithography. This results in the formation of a variety of active and passive components near one surface of the wafer. These components are connected together by means of thin film wiring and generally are present at several levels separated by inter-metal dielectric layers. Usually, the topmost layer is made of dielectric and serves as a passivation layer for the entire structure.
An ongoing problem associated with integrated circuit technology is the electrical isolation of various components and/or sub circuits from one another. An early technique developed to solve this problem was LOCOS (local oxidation of silicon) wherein thick layers of oxide were formed locally. More recently this has been replaced by shallow and deep trench isolation. In this technique, trenches with near vertical sides are etched between the circuits and then filled with dielectric materials. This approach has the advantage of consuming less space between circuits than LOCOS does.
However, even deep trench isolation is not fully satisfactory when full isolation between circuits is required. This is particularly true when high speed analog circuits are involved. One approach to dealing with this has been the technology known as silicon on insulator (SOI) where the substrate that supports the integrated circuits is a sheet of insulator rather than the semiconductor material that forms the rest of the wafer beneath the active regions. A number of techniques for achieving this are in use including silicon on sapphire (SOS) where a layer of silicon is grown epitaxially on a sheet of sapphire.
SOS and other techniques such as FIPOS (Field isolation by porous silicon) or ion implanting oxygen beneath the active region are, in general, very expensive to implement. In addition, they suffer from a number of drawbacks that derive from the very fact that the insulator in SOI is too good (DC-wise)! For example, the entire semiconductor layer is now electrically floating and therefore subject to charge accumulation. Also, since the semiconductor layer is relatively thin, under some circumstances it may be prematurely consumed through oxidation. Yet another problem is power dissipation because of the poor thermal conductivity of the insulator even though SOI circuits can usually be operated at lower power. Additional problems associated with conventional SOI include vulnerability to electrostatic discharges and snapback in the device I-V characteristics. These arise because the electrically floating silicon film would accumulate static charge and eventually discharge and cause damage to devices built on it. In a similar fashion, a dynamic charge overload on the floating silicon film can cause local breakdown and thus decrease of device operating voltage while increasing its current.
A method to achieve full circuit isolation, of analog and digital regions, without the need to use SOI has been described by the present inventor and one other in patent application #081998/734, filed Dec. 29, 1997. They describe the formation of semi-insulating regions in a semiconductor through bombardment with a high energy particle beam, including protons. These semi-insulating regions extend through the full thickness of the wafer so relatively high energy radiation (15-30 Mev for protons) must be used. The invention also teaches use of a mask made of Al, Fe, or W and having a thickness between 0.1 and 2 mm.
In the course of searching the patent literature we did not come across any references that teach a solution to the problem of full isolation that is similar to that disclosed in the present invention. However, a number of references of interest were encountered. For example, Dixon et al. (U.S. Pat. No. 4,124,826 November 1978) form high resistivity zones within a gallium arsenide laser by means of proton bombardment. Proton energies of about 300 keV were used at a fluence of 3.times.10.sup.15 /cm.sup.2. The penetration depth was about 2.4 microns.
Voss (U.S. Pat. No. 4,987,087 January 1991) teaches the use of a mask during proton bombardment of a semiconductor. Proton energy was 2-6 MeV at a fluence of 10.sup.11 -10.sup.13 /cm.sup.2. A key feature of the Voss process is an annealing step (250-350.degree. C. for at least two hours) after proton bombardment.
Adam et al. (U.S. Pat. No. 4,806,497 February 1989) bombarded a semiconductor with several different ion species, including protons. Each species serves a different purpose, the protons being used to create recombination centers with a view to adjusting carrier lifetime. No details, such as penetration depth, particle energies, etc. are provided.